This invention relates to line memories used in the field of image processing, particularly line memories for speed conversion at different input and output data rates.
FIG. 1 illustrates configuration of conventional line memories for speed conversion and FIG. 2 their time charts in which the exemplified output data rate is as high as twice the input data rate.
In FIG. 1, serially input data D.sub.in enters a 1:n (n is an integer) serial-parallel conversion circuit 3 through input buffer 2 in order to reduce the actual operation speed of memory cell 1. The output of conversion circuit 3 whose operation speed has become 1/n is entered in memory cell 1 and is written in a memory region having a write address assigned by write address pointer 4. The write address pointer 4 operates by a write clock WCK and increases the write address at every output timing of conversion circuit 3, resets the write address to "0" by write address reset signal WR entered at every interval of a predetermined number of cycles of write address increase, and starts a new write cycle.
The data written in memory cell 1 is read out in the order of the address assigned by read address pointer 5. Address pointer 5 is operated by a read clock RCK and increases read addresses in cycles shorter by the ratio of input and output data rates than cycles of write address increase, and resets read address to "0" by a read address reset signal RR entered at every interval of a predetermined number of cycles of read address increase, and starts a new read-out cycle.
Memory cell 1 has two memory areas (not illustrated) which contain the same number of memory regions. On this memory cell the write is made alternately in two memory areas and the read-out in the memory area where write is not made. When the ratio of output data D.sub.out to input data D.sub.in is, for example, two, the read-out speed is twice the write speed. The read-out cycle is therefore repeated twice in one write cycle. In this case, after a write cycle starts at the time when a write address-reset signal WR is entered, the write cycle and two read-out cycles finish at the time when the second read address reset signal RR is entered, and the area to be written and the area to be read out are interchanged.
The data read out from memory cell 1 is entered into a n:1 parallel-serial conversion circuit 6. The output of conversion circuit 6, operation speed of which comes to N times the read-out speed of memory cell 1, is sent out serially as output data D.sub.out through output buffer 7.
The above mentioned operation is described in detail with reference to the time chart in FIG. 2. As shown in FIG. 2(a), usually a write reset signal WR and a read reset signal RR are fed simultaneously, and at this point of time input data D.sub.in (e.g. B.sub.1, B.sub.2, . . . , B.sub.m) starts to be written in one side area of memory cell 1, while readout of previously written input data (e.g. A.sub.1, A.sub.2, . . . , A.sub.m) from the other side area starts. Since, as mentioned above, the read-out speed is twice the write speed, the read-out cycle of previously written input data A.sub.1, A.sub.2, . . . , A.sub.m is repeated twice during the write cycle of new input data B.sub.1, B.sub.2, B.sub.m. At the input time of second read address reset signal RR after write address reset signal WR, memory areas of write and read-out interchange, read of data B.sub.1, B.sub.2, . . . , B.sub.m out of the area in Which data is previously written starts, and write of next input data C.sub.1, C.sub.2, . . . , C.sub.m into the area at which data has been read out previously starts.
FIG. 2(b) is a time chart in which timing of output data D.sub.out is shifted from FIG. 2(a). In such a case, input timing of read address reset signal RR is shifted as shown in the time chart. This operation shifts the output data timing by the same quantity of the shift of read address-reset signal RR.
As mentioned above, in conventional technique, when required to shift the timing of output data, read address-reset signal RR is shifted by the same quantity as the above shift. When read address signal RR is shifted in such a way, the time lag between write address reset signal WR and read address reset signal RR occurs as shown in the time chart of FIG. 2(b). For example, read address reset signal RR precedes write address reset signal WR by two-clock input data D.sub.in in the time chart of FIG. 2(b). In this case, as described above, since memory areas of write and read interchange at the time of input of the second read address reset signal RR (e.g. read address reset signal RR at the left end of the time chart) after write address reset signal WR, data A.sub.m-1 and A.sub.m that are written after input time of left-end read address reset signal RR are written in areas which differ from that of data A.sub.1, A.sub.2, A.sub.m-2 which have been written previously. Consequently, data A.sub.m-1, A.sub.m are not read out and different data (data shown with "X" in the time chart) after data A.sub.1, A.sub.2, . . . , A.sub.m-2 are read out in read-out cycle which starts with left-end read address reset signal RR. The same as above occurs in all readout cycles. When read address reset signal RR is shifted as above, the time lag occurs between write address-reset signal WR and read address reset signal RR, and it happens as a problem that data written during the period of this time lag disappears from output data.
Furthermore, in order to increase operation speed of line memory, the 1:n serial-parallel conversion is made at write as mentioned above and write in memory cell is made at every n clock input data D.sub.in. In this case, to prevent interchange of memory areas of write and read during write in a certain address, a time lag between read address reset signal RR and write address reset signal WR should be equal to the increased period of read address or should be an integer multiple of it. Therefore, read address reset signal RR must be shifted in unit of n-clock input data D.sub.in, and consequently data output timing must be shifted only in unit of n-clock input data D.sub.in.